Home News Here is what Intel unveiled during the Architecture Day 2020: Tiger Lake...

Here is what Intel unveiled during the Architecture Day 2020: Tiger Lake CPUs, Xe Graphics, 10nm SuperFin Process and more

Intel, during its virtual Architecture Day 2020 seminar made significant disclosures about the details of its upcoming products, especially in the department of  CPU and GPU. At the  Architecture Day 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making on its six pillars of technology innovation: process and packaging, architecture, memory, interconnects, security and software.

According to the company, it will be taking full advantage of its unique position to deliver a mix of scalar, vector, matrix and spatial architectures deployed in CPUs, GPUs, accelerators and FPGAs – unified by one API, an industry-standard open programming model to simplify application development. This year the company hosted a virtual event where it showcased its 10nm SuperFin technology in order to represent the largest single internode enhancement ever done by the company and to deliver performance improvement compared to a full-node transition. 

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In addition to this, the company has also revealed details related to its Willow Cove microarchitecture and the Tiger Lake system-on-chip architecture for mobile clients.

To start with, the 10nm SuperFin Technology combines Intel’s enhanced FinFET transistors with a Super metal insulator metal capacitor. This tech brings improved epitaxial source/drain, improved gate process and additional gate pitch to enable greater performance by enhancing epitaxial growth of crystal structures on the source and drain to increase strain while reducing resistance to allow more current through the channel. Also, it can improve the gate process to drive higher channel mobility, which enables charge carriers to move more quickly—at the same time, providing an extra gate pitch option for higher drive current in certain chip functions that require the utmost performance. This uses a novel thin barrier to reduce resistance by 30% and enhance interconnect performance. In addition to this, the 10nm SuperFin technology can deliver a 5x increase in capacitance within the same footprint when compared to industry standard, driving a voltage droop reduction that translates to dramatically improved product performance. 

However, the company’s upcoming mobile processor, code-named Tiger Lake, is based on 10nm SuperFin technology and at the moment is in the pipeline and is expected to be shipped during the US holiday season this year.

Whereas the Willow Cove is Intel’s upcoming CPU microarchitecture which is based on the latest process advancements, 10nm SuperFin technology and the foundation of the Sunny Cove architecture. Intel’s next-generation CPU microarchitecture is capable of providing a generational increase in CPU performance with large frequency improvements and increased power efficiency with redesigned caching architecture to a larger non-inclusive 1.25MB MLC and security enhancements with Intel Control-Flow Enforcement Technology.

According to the company, Tiger Lake SoC architecture will be offering the new Willow Cove CPU core with significant frequency uplift leveraging 10nm SuperFin technology advancements. The latest Xe graphics with up to 96 execution units (EUs) with significant performance-per-watt efficiency improvements. For power management, the – autonomous dynamic voltage frequency scaling in coherent fabric, increased fully integrated voltage regulator efficiency.

Fabrics and memory – 2x increase in coherent fabric bandwidth, ~86GB/s memory bandwidth, validated LP4x-4267, DDR4-3200; LP5-5400 architecture capability and Gaussian Network Accelerator (GNA) 2.0 dedicated IP for low-power neural inferencing offloading from the CPU. ~20% lower CPU utilisation on GNA vs CPU (running noise suppression workload). Along with the integration of TB4/USB4, integrated PCIe Gen 4 on CPU for low-latency, high-bandwidth device access to memory with a display of up to 64GB/s of isochronous bandwidth to memory for multiple high-resolution displays. In addition to six sensors with 4K30 video, 27MP image, up to 4K90 and 42MP image architectural capability.

Although the company is refining its hybrid architecture with Alder Lake, the company’s next-generation client product together with two upcoming architectures: Golden Cove and Gracemont, optimised to offer great performance per watt. 

During the Architecture 2020 event, the company has also detailed the Xe-LP (low power) microarchitecture. The company’s in-house GPU will come with up to 96 EUs and new architecture designs. These include asynchronous compute, view instancing, sampler feedback, updated media engine with AV1 and updated display engine to enable new end-user features with instant game tuning, capture, and stream-and-image sharpening. On software optimisation, Xe-LP will have driver improvements with a fresh DX11 path and optimized compiler. 

 

Intel touts that its first Xe-HP chip is multi-tiled, highly scalable, high-performance architecture, providing data centre-class, rack-level media performance, GPU scalability and AI optimization. 

The company is now sampling Xe-HP with key customers and plans to enable it in Intel DevCloud for developers. Xe-HP will be available next year. The company has also introduced a Xe microarchitecture variant. Over that the Xe-HPG and a gaming-optimized microarchitecture are also on the cards. These bring good performance-per-watt building blocks from Xe-LP, leveraging the scale from Xe-HP for a more significant configuration and compute frequency optimisation from Xe-HPC. A new memory subsystem based on GDDR6 is added to improve performance per dollar and XeHPG will have accelerated ray tracing support. Xe-HPG is expected to start shipping in 2021.

For the data centres, the next-gen Xeon Scalable processor based on Ice Lake SP architecture is expected to be ship later this year bringing a set of technologies. This includes total memory encryption, PCIe Gen 4 and eight memory channels with instruction-set architecture to speed up crypto processing. While the Sapphire Rapids is Intel’s next-generation Xeon Scalable processor based on enhanced SuperFin technology will include DDR5, PCIe Gen 5 and Compute Express Link 1.1. Sapphire Rapids will be the CPU used in the Aurora Exascale supercomputer system at Argonne National Lab. Sapphire Rapids is expected to start initial production shipments in the second half of 2021.

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Komila Singhhttps://www.gadgetbridge.com
Komila is a one of the most spirited tech writers at Gadget Bridge. Always up for a new challenge, she is an expert at dissecting technology and getting to its core. She loves to tinker with new mobile phones, tablets and headphones.

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